Commutation cells are commonly used in electronic systems that require conversion of a voltage source including both DC-DC converters and DC-AC converters, which are often called inverters. With the limited space allowed for power converter circuits, such as those used for example in electric and/or electric hybrid automotive applications and given the high cost of the semi-conductors, the demand for integration of these commutation cells increases.
A known way of reducing the space occupied by semiconductors in power converter circuits is to increase their efficiency to thereby allow the size of their cooling surface to be reduced.
Losses in power electronic switches present in conventional power converter circuits are mainly caused by two sources; conduction losses and switching losses. One way to reduce switching losses is generally by accelerating the turn-on and turn-off of the power electronic switches. However, fast turn-off of the power electronic switches generates overvoltage in parasitic (stray) inductances of their high-frequency loop. It is thus often required to slow down turning off of the power electronic switches to protect them against overvoltage. This may seriously impact the overall efficiency of conventional power converter circuits.
FIG. 1 is an idealized circuit diagram of a conventional commutation cell such as those used in conventional power converter circuits. A commutation cell 10 converts a DC voltage Vbus from a voltage source 12 (or from a capacitor) into a current source Iout (or into an inductance) that usually generates a voltage Vout appropriate for a load 14, which may be a resistive load an electric motor and the like. The commutation cell 10 comprises a freewheel diode 16 and a controlled power electronic switch 18, for example an isolated gate bipolar transistor (IGBT). A capacitor 20 (Cin) is used to limit variations of the voltage Vbus of the voltage source 12 and an inductance 32 is used to limit the variations of the output current Iout. A gate driver (not shown in FIG. 1 but shown on later Figures) controls turning on and off of the power electronic switch 18. FIG. 1 illustrates a configuration of the commutation cell 10 of the load 14 and of the voltage source 12, in which energy flows from the voltage source 12 to the load 14, i.e. from left to right on the drawing. The commutation cell 10 can also be used in a reverse configuration in which energy flows in the opposite direction.
When turned on, the power electronic switch 18 allows current to pass therethrough, from its collector 22 to its emitter 24; at that time, the power electronic switch 18 can be approximated as a closed circuit. When turned off, the power electronic switch 18 does not allow current to pass therethrough and becomes an open circuit.
The gate driver applies a variable control voltage between the gate 26 and the emitter 24 of the power electronic switch 18. For some types of power electronic switches such as bipolar transistors, the gate driver may act as a current source instead of as a voltage source. Generally, when the voltage applied between the gate 26 and the emitter 24 is “high”the power electronic switch 18 allows passing of current from the collector 22 to the emitter 24. When the voltage applied between the gate 26 and the emitter 24 is “low”the power electronic switch 18 blocks passage of current therethrough. In more details, a voltage difference between the gate 26 and the emitter 24, denoted Vge, is controlled by the gate driver. When Vge is greater than a threshold Vge(th) for the power electronic switch 18, the switch 18 is turned on and a voltage Vce between the collector 22 and the emitter 24 becomes near zero. When Vge is lower than Vge(th), the power electronic switch 18 is turned off and Vce eventually reaches Vbus.
When the power electronic switch 18 is turned on, a current Iout flows from the voltage source 12 (and transiently from the capacitor 20) through the load 14 and through the collector 22 and the emitter 24. When the power electronic switch 18 is turned off, the current Iout circulates from the load 14 and passes in the freewheel diode 16. It may thus be observed that the power electronic switch 18 and the freewheel diode 16 operate in tandem. Turning on and off of the power electronic switch 18 at a high frequency allows the current Iout, in the output inductance Lout 32, to remain fairly constant.
It should be observed that, in the case of other power electronic switch types for example bipolar transistors, the term “gate” may be replaced with “base”, the base being controlled by a current as opposed to the gate that is controlled by a voltage. These distinctions do not change the overall operation principles of the commutation cell 10.
FIG. 2 is another circuit diagram of the conventional commutation cell of FIG. 1, showing parasitic (stray) inductances. In contrast with the idealized model of FIG. 1, connections between components of an actual commutation cell define parasitic inductances. Though the parasitic inductances are distributed at various places within the commutation cell 10, a suitable model presented in FIG. 2 shows two (2) distinct inductances representing the overall parasitic inductance including an emitter inductance 30 of the power electronic switch 18 and an inductance 34 representative of all other parasitic inductances (other than the emitter inductance 30) around a high frequency loop 36 formed by the freewheel diode 16, the power electronic switch 18 and the capacitor 20. The high frequency loop 36 is a path where current changes significantly upon switching of the power electronic switch 18. It should be noted that an output inductance Lout 32 is not part of the high frequency loop because its current remains fairly constant through the commutation period.
FIG. 3 is a circuit diagram of a conventional commutation cell further showing a gate driver 40. Some elements of the commutation cell 10 are not shown on FIG. 3 in order to simply the illustration. FIG. 3 further shows a gate driver 40 having a positive supply voltage 42 and a negative supply voltage 44, an output 46 of the gate driver 40 being connected to the gate 26 of the power electronic switch 18 via a gate resistor Rg. The positive supply voltage 42 of the gate driver 40 has a value denoted +Vcc while the negative supply voltage 44 has value denoted −Vdd. An input 48 of the gate driver 40 is connected to a controller (not shown) of the commutation cell 10, as is well known in the art. A voltage at the output 46 of the gate driver 40 goes up to +Vcc and goes down to −Vdd in order to control the voltage at the gate 26. The input resistance of the gate 26 to emitter may be very high, especially in the case of an IGBT. However, a parasitic Miller capacitance present between the gate 26 and the emitter 24, causes some current to flow from the output 46 when the gate driver 40 alternates between +Vcc and −Vdd. The value Rg of the gate resistor is selected as a function of the parasitic Miller capacitance and of a desired switching rate of the power electronic switch 18 so that the voltage at the gate 26 changes at rate appropriate for the desired switching rate.
On FIG. 3, a current Iigbt flowing through the power electronic switch 18 and through the emitter parasitic inductance 30 is essentially equal to Iout when the power electronic switch 18 is turned on and quickly reduces to zero (substantially) when the power electronic switch 18 turns off.
When the power electronic switch 18 turns on or off the current Iigbt flowing therethrough increases or diminishes at a fast rate. These variations of Iigbt, denoted di/dt, generate voltage across inductances 30 and 34, according to the well-known equation (1):
                              V          L                =                  L          ·                                    d              ⁢                                                          ⁢              i                                      d              ⁢                                                          ⁢              t                                                          (        1        )            
wherein VL is a voltage induced across an inductance and L is an inductance value.
A voltage VLs is generated across the parasitic inductance 34 and a voltage VLe is generated across the emitter parasitic inductance 30. On FIGS. 2 and 3, the polarities shown across the high frequency loop inductance 34, including the emitter inductance 30 reflect voltages obtained upon turn-off of the power electronic switch 18 when the Iigbt current diminishes very rapidly, di/dt thus taking a negative value. Upon turn-on of the power electronic switch 18 voltages across the high frequency loop inductance 34, including the emitter inductance 30 are in the opposite direction.
These voltages VLs and VLe are in series with Vbus from the voltage source 12. When the power electronic switch 18 turns off the collector 22 to emitter 24 voltage increases until the freewheel diode 16 turns on. At that time addition of Vbus, VLs and VLe results in an important overvoltage applied between the collector 22 and the emitter 24 of the power electronic switch 18. Though power electronic switches are rated for operation at some level of voltage, extreme overvoltage can reduce the lifetime of any power electronic switch to thereby lead to its premature failure or even break the device.
FIG. 4 is a circuit diagram of a conventional IGBT leg formed of two conventional commutation cells. Two commutation cells 10 introduced in the above description of FIGS. 1-3, in which IGBTs are used as power electronic switches 18 in the example of FIG. 4 are connected in a single loop to form an IGBT leg 70 of a power converter 50. A first power electronic switch (bottom IGBT Q1) operates in tandem with a first freewheel diode (top freewheel diode D2) and a second power electronic switch (top IGBT Q2) operates in tandem with another freewheel diode (bottom freewheel diode D1). Each IGBT has its own gate driver 40. A voltage source 12 provides a voltage Vbus in parallel to an input capacitance 20 (Cin) connected to the IGBT leg 70 via a parasitic inductance Lc. Parasitic inductances inherently provided in wires connections decoupling capacitor and circuit board traces of a power converter have been represented in FIG. 4. A three-phase power converter used for powering a three-phase electric motor (not shown) from a battery such as 12, would comprise three (3) IGBT legs 70 as shown on FIG. 4. Since such three-phase power converters are believed well-known they are not described in further details herein.
As can be seen from FIG. 4, a reference of each gate driver is connected to the emitter of the IGBT Q1 and Q2, typically known as logical pins of the IGBTs Q1 and Q2. For concision purpose a description of FIG. 4 focuses on its bottom portion including the bottom IGBT Q1.
The overvoltage effect on a power electronic switch 18 discussed in the above description of FIGS. 2 and 3, also applies to the IGBTs Q1 and Q2.
When the bottom IGBT Q1 is turned off current transits from the bottom IGBT Q1 to the top freewheel diode D2, during an overvoltage period. A properly selected IGBT is able to support the overvoltage created by a current variation (di/dt) across various parasitic inductances (Lc, L+Vbus, Lc-high, Le-high, Lc-low, Le-low and L−Vbus) present in the IGBT leg 70. Indeed, since the inductances resist change of current therein, additive voltages develop in the IGBT leg 70 as illustrated by the polarities of the parasitic inductances shown on in FIG. 4. These voltages, added to the voltage Vbus of the source, often result in a voltage exceeding the maximal collector to emitter voltage Vce rating of the bottom IGBT Q1. The top IGBT Q2 is subject to the same problem.
Solutions exist that tend to limit overvoltage in power electronic switches by slowing down the slope of the gate-emitter voltage. However excessive limitation of the overvoltage can imply longer switching times of the current, reducing commutation cell performance.
Also, the commutation cell 10 and the power converter 50 can deliver their maximum power when operating at high bus voltages Vbus. Current solutions to limit the overvoltage generated across the parasitic inductances of the high frequency loop 36 allow using bus voltages approaching the maximum voltage rating of the power electronic switches 18. However, bus voltages may vary over time or between different applications. For those reasons, overvoltage protection in conventional commutation cells generally need to be overdesigned, as a safety measure. As such, conventional commutation cells operate at less than their maximum attainable power output.
Numerous additional problems related to dynamic current sharing arise from parallelization of commutation cells particularly when placing IGBT legs in parallel. For example should one of a pair of parallelized power electronic switch transition being states faster than the other of the same pair this fastest switch supports more current than the others and therefore generates more heat. This often leads to premature ageing of some of the parallelized power electronic switches, leading to the premature end of life of power converters.
Conventionally, to overcome such dynamic unbalance problems, some rules are followed. A first rule suggests using a matching gate driver circuit for each power electronic switch, in which gate drivers having equal gate resistors as well as gate loop inductance are used to minimize the delays between the switching times of all the power electronic switches. According to a second rules, power electronic switches to be placed in parallel are selected so that they have matched intrinsic parameters such as parasitic capacitances, threshold voltage and gain. Selection of matched power electronic switches may be made by using switches manufactured in a same batch. Finally, a third rule suggests using identical circuit layouts in the high frequency loop for every power electronic switch.
It is often particularly difficult to fulfill this third rule, in many applications, since common power electronic switch have their own power circuit paths. Also, when placing discrete switches in parallel, it is not always possible to match each of their power circuit branches because of mechanical and packaging imperatives.
Therefore, there is a need for circuits capable of compensating for variable characteristics of power electronic switches.